The present invention relates to a power supply voltage detection device for detecting abrupt variations in power supply voltage due to external noise and the like in an apparatus such as a microcomputer.
A conventional apparatus such as a microcomputer malfunctions owing to abrupt variations in power supply voltage. For this reason, a power supply voltage detection circuit detects that the power supply voltage falls outside a rated range, and the apparatus is reset upon detection of a power supply voltage variation.
FIG. 6 shows a conventional power supply voltage detection circuit. Referring to FIG. 6, the power supply voltage detection circuit is constituted by a lower limit comparator 11 for detecting when a power supply voltage VDD becomes equal to or lower than a rated lower limit Vref1, an upper limit comparator 12 for detecting when the power supply voltage VDD becomes equal to or higher than a rated upper limit Vref2, an AND gate 13 for ANDing an output VO11 from the lower limit comparator 11 and an output VO12 from the upper limit comparator 12, and resistors R11 and R12.
A reference voltage Vref1' input to the lower limit comparator 11 and a reference voltage Vref2' input to the upper limit comparator 12 are set with respect to the rated lower limit Vref1 and the rated upper limit Vref2 of the power supply voltage VDD as follows: EQU Vref1'=Vref1.times.R12/(R11+R12) EQU Vref2'=Vref2.times.R12/(R11+R12)
The operation of the power supply voltage detection circuit having the above arrangement will be described with reference to FIGS. 7A to 7D. Referring to FIG. 7A, when the power supply voltage VDD abruptly drops to become equal to or lower than the rated lower limit Vref1 owing to external noise or the like, the output VO11 from the lower limit comparator 11 is set at "L" level (Low level), as shown in FIG. 7B. As a result, an output VO13 from the AND gate 13 is also set at "L" level.
When the power supply voltage VDD abruptly rises to become equal to or higher than the rated upper limit Vref2, the output VO12 from the upper limit comparator 12 is set at "L" level, as shown in FIG. 7C. As a result, the output VO13 from the AND gate 13 is also set at "L" level, as shown in FIG. 7D. That the power supply voltage VDD becomes equal to or lower than the rated lower limit Vref1 or equal to or higher than the rated upper limit Vref2 can be detected in this manner.
Some apparatus such as a microcomputer operates in a wide operating voltage range and can be used with a plurality of power supply voltage ratings (e.g., operable at power supply voltages VDD of 5 V, 3 V, . . .). Obviously, in this case, when the power supply voltage VDD is changed, the rated lower limit Vref1 and the rated upper limit Vref2 also vary accordingly.
In the conventional power supply voltage detection circuit, however, the reference voltage Vref1' for detecting when the power supply voltage VDD becomes equal to or lower than the rated lower limit Vref1 must be applied, together with the reference voltage Vref2' for detecting when the power supply voltage VDD becomes equal to or higher than the rated upper limit Vref2. For this reason, when the rating of the power supply voltage VDD changes, the reference voltages Vref1' and Vref2' must be set again in accordance with the rated lower limit Vref1 and the rated upper limit Vref2.
Although this circuit is designed to detect abrupt variations in power supply voltage due to external noise and the like, the circuit also detects moderate variations in power supply voltage (the output VO13 from the AND gate 13 is set at "L" level) during a power-on period (a period PON in FIGS. 7A to 7D) or power-off period.